1. Field of the Invention
The present invention is related to the field of electronic design automation (EDA) and more particularly to the field of interface synthesis for intellectual property (IP) blocks.
2. Description of Background Art
As time to market pressures and product complexities climb, the pressure to reuse complex building blocks (also known as Intellectual Property, or IP) also increases. Today, most IP is available only at the register transfer level (RTL). This is problematic because of verification speeds and the variety of signaling conventions used for interfacing between IP blocks.
The present invention addresses the problem of synthesizing interfaces between communicating IPs that use different signaling conventions. For this problem, a description of the entire behavior of the IP is not only cumbersome, but introduces unnecessary details that may hamper the design process. An interface-based design process that attempts to separate the communication from the behavior for IP is described in J. A. Rowson and A. L. Sangiovanni-Vincentelli, Interface Based Design, Proceedings of the 34th Design Automaton Conference, 178–183 (Jun. 9–13, 1997) which is incorporated by reference herein in its entirety. To separate the communication aspect of the IP blocks from their behavior, the blocks must be abstracted to a transaction or messaging level. With abstracted communication, improvement in simulation performance was shown with a simulator named Cheetah. However, the abstraction level that is appropriate for fast simulation is not efficient for implementation.
One problem is that given two communicating design actors exchanging data, e.g., IP blocks, and a description of the two protocols that each one of the IP blocks uses to transfer the data, an interface needs to be generated that ensures that data transfers are consistent between the two protocols.
Some conventional systems have attempted to address the problem of interface synthesis. One such conventional system is described in G. Borriello, A New Interface Specification Methodology and its Applications to Transducer Synthesis, Ph.D. Thesis, University of California at Berkeley, Berkeley Calif. (1988) and G. Borriello and R. H. Katz, Synthesis and Optimization of Interface Transducer Logic, Proceeding of the International Conference on Computer Aided Design (November 1987), which are both incorporated by reference herein in their entirety (together referred to as “Borriello”. Borriello introduces an “event graph” to establish synchronization between the two protocols and data sequencing. One limitation of this approach is that before attempting to make the two protocols compatible, a user must manually assign labels to the data referenced by each protocol, because the specification of the protocols is given at a very low level of abstraction using waveforms.
A second conventional system is described in J. S. Sun and R. W. Brodersen, Design of System Interface Modules, Proceeding of International Conference on Computer Aided Design, 478–481 (1992) which is incorporated by reference herein in its entirety. This second system extends the Borriello approach by providing a library of components. Each component in the library must still be manually entered into the library. Accordingly, even in this second system the user must still consider lower level details.
A third approach is described in S. Narayan and D. D. Gajski, Interfacing Incompatible Protocols Using Interface Process Generation, Proceedings of the 32nd Design Automation Conference, 448–473 (Jun. 12–16, 1995) which is incorporated by reference herein in its entirety. In this approach the protocol specification is first reduced to the combination of five basic operations (data read, data write, control read, control write, and time delay). Then the protocol description is broken into blocks (called relations) whose execution is guarded by a condition on one of the control wires or by a time delay. Next, the relations of the two protocols are matched into sets that transfer the same amount of data. Although this approach is able to account for data width mismatch between the two modules, the procedural specification of the protocols makes it difficult to adapt different data sequencing.
Another conventional approach is described in J. Akella and K. McMillan, Synthesizing Converters Between Finite State Protocols, Proceedings of the International Conference on Computer Design, 410–413 (Oct. 14–15, 1991) which is incorporated by reference herein in its entirety. In this approach the protocols are described as two finite state machines (FSMs), while a third FSM represents the valid transfer of data. The product machine is taken and pruned of the invalid/useless states. One limitation in this conventional approach is that data width mismatch cannot be handled and that the designer must manually enter the intended behavior of the interface in the form of the third FSM (referred to as the C-machine).
What is needed is a system and method that overcomes the above identified limitations and: (1) automatically resolves the correspondence between data referenced by multiple protocols; and (2) generates an interface that can translate between different sequences of data without having to manually introduce the intended behavior of the interface process.